This invention relates to a method for planarizing dielectric films between conductive layers on semiconductor wafers which are for use in the fabrication of integrated circuits.
The increase of circuit density on silicon chips necessitates increased ability to interconnect large numbers of integrated silicon devices on a single chip. The dimensional limitation of the active area in an integrated circuit dictates that vertical interconnections be made by means of multilevel metallization. As the circuits become denser, and the feature sizes smaller, the topography becomes too sever for conventional multilevel metallization structures to provide acceptable yield or to have acceptable reliability. It has been found that planarizing the dielectric between the metal interconnect layers improves the metal patterning and step coverage. This improved metal patterning and step coverage allows the use of multilevel metallization of large scale (LSI) and very large scale (VLSI) integrated circuits.
Recently, polyimide has been used to provide a flat surface for the next level of metallization as described in an article entitled "Process for Forming Passivated Metal Interconnection System with a Planar Surface" by L. B. Rothman published in the Journal of the Electrochemical Society: Solid State Science and Technology, Volume 130, Number 5, May 1983. However, one drawback of using polyimide is that in order to achieve planarization, a relatively thick layer of polyimide (e.g., 2.0 microns) must be used. It is difficult to etch small vias (&lt;3.0 microns) through this thick dielectric and even more difficult for metal to cover these deep via holes. There are also concerns about the polyimide adhering to the wafer and subsequent films adhering to the polyimide resulting in potential yield and reliability problems.
Another planarization technique described in an article entitled "A New Application of RIE to Planarization and Edge Rounding of SiO.sub.2 Hole in the Al Multi-level Interconnection" by Y. Hazuki, T. Moriya and M. Kashiwagi published in the 1982 Symposium on VLSI Technology, uses reactive ion etching (RIE) to provide a flat surface for the next level of metallization. A layer of SiO.sub.2 and SiN is deposited over the first level of metallization. Then a RIE is performed using CF.sub.4 +H.sub.2 which etches the SiN and SiO.sub.2 at the same rate. The etch is stopped when all of the SiN is removed. After the RIE, a 1.0 micron thick SiO.sub.2 layer is deposited. One limitation of this process is that planarization only occurs where the steps are spaced close together (i.e. &lt;2.0 microns). Thus, steps that are not spaced close together will not benefit from this planarization technique. Furthermore, after the planarization another deposition of silicon dioxide is required which adds processing time and complexity.
Additionally, a planarization technique described in an article entitled "Plasma Planarization" by A. C. Adams, published in Solid State Technology, April 1981, disclosed the deposition of a single layer of SiO.sub.2 over the first level of metal which is then coated with a layer of resist. Since the surface of the resist is almost flat, the resist is thinner over the metal steps. Plasma etching is then performed in such a way that the etch rates of the resist and the dielectric are equal. As the unpatterned resist is etched, the dielectric on top of the metal steps is removed but the dielectric between the metal steps is protected by the resist. Stopping the etch when all of the resist is removed results in a nearly flat surface for the next level of metal. One drawback of this process is that on an actual integrated circuit not all of the metal steps are at the same height because of the underlying topography, thus the dielectric above a metal line that forms a high step (i.e., metal over polysilicon) will be much thinner than the dielectric over a metal line that forms a smaller step (e.g., metal over an island area). Therefore, the minimum dielectric thickness between the metal levels is dependent upon the underlying topography and how well the planarization etch is controlled, which makes this process highly susceptible to shorts between the metal layers. Also, in this process the etch attacks the dielectric that is to be the electrical insulator between the metal layers which can cause pin holes resulting in shorts between metal layers.